1. Field of Invention
The invention relates to a method for selectively etching a pattern in an insulation stack and, in particular, a method for selectively etching a trench-via structure in a low dielectric constant (low-k) insulation stack for subsequent metallization.
2. Description of Related Art
As is known to those in semiconductor device manufacturing, interconnect delay is a major limiting factor in the drive to improve the speed and performance of integrated circuits (IC). One way to minimize interconnect delay is to reduce interconnect capacitance by using low dielectric constant (low-k) materials and ultra-low-k dielectric materials in metal interconnects during back-end-of-line (BEOL) operations for IC production. Such low-k materials presently include organosilicon glass or SiCOH-containing materials.
Thus, in recent years, low-k materials have been developed to replace relatively high dielectric constant insulating materials, such as silicon dioxide. In particular, low-k materials are being utilized for inter-level and intra-level dielectric layers between metal layers of semiconductor devices. Additionally, in order to further reduce the dielectric constant of insulating materials, material films are formed with pores, i.e., porous low-k dielectric materials. Such low-k materials can be deposited by a spin-on dielectric (SOD) method similar to the application of photoresist, or by chemical vapor deposition (CVD). Hence, the use of low-k materials is readily adaptable to existing semiconductor manufacturing processes.
When preparing a new interconnect level on a semiconductor substrate, a cap layer is typically formed overlying the preceding interconnect layer, followed by the formation of the low-k insulation layer and one or more layers, such as a hard mask, overlying the low-k insulation layer. Upon formation of the insulation stack, lithography and etch processing are utilized to pattern the insulation layers in preparation for subsequent metallization processes. For example, the insulation layer stack may be patterned with a trench-via structure according to various integration schemes, including dual damascene integration, when preparing a metal line and contact plug to provide electrical continuity between one interconnect layer and an adjacent interconnect layer.
However, the practical implementation of low-k materials in insulation layer stacks for metal interconnects poses many challenges. One challenge includes selectively patterning the insulation layer stack without damage to the underlying interconnect layer while achieving specified critical dimensions (CDs) for the trench and via structures. During the patterning of the low-k insulation layer, it is essential that the etch process does not prematurely penetrate the underlying cap layer.